use moparse_lib::VerilogParser;

fn main() {
    let parser = VerilogParser::new();
    
    // Test the signal extraction
    let test_expr1 = "{TX_P,TX_N}";
    let test_expr2 = "{RX_P,RX_N}";
    
    println!("Testing signal extraction:");
    println!("Expression: {}", test_expr1);
    let signals1 = parser.extract_signal_names(test_expr1);
    println!("Extracted signals: {:?}", signals1);
    
    println!("Expression: {}", test_expr2);
    let signals2 = parser.extract_signal_names(test_expr2);
    println!("Extracted signals: {:?}", signals2);
    
    // Check if top ports contain these signals
    let top_ports = vec!["TX_P", "TX_N", "RX_P", "RX_N"];
    println!("Top ports: {:?}", top_ports);
    
    for signal in &signals1 {
        if top_ports.contains(&signal.as_str()) {
            println!("Signal {} is in top ports", signal);
        } else {
            println!("Signal {} is NOT in top ports", signal);
        }
    }
    
    for signal in &signals2 {
        if top_ports.contains(&signal.as_str()) {
            println!("Signal {} is in top ports", signal);
        } else {
            println!("Signal {} is NOT in top ports", signal);
        }
    }
}